System-on-Chip integrated circuits are becoming ever more popular in various applications including embedded applications in one or more devices such as set-top-boxes, mobile phones, portable media devices, Personal Digital Assistant (PDA), computers and so on. The SoC is configured with Central Processing Unit (CPU), memory unit, peripheral controllers corresponding to one or more peripherals connected to the one or more devices, bus interfaces and other units which are presently configurable in the SoCs. The peripheral controllers operate the peripherals connected to the SoC. For example, a display controller operates functionality of a display unit and a keyboard controller operates functionality of a keyboard. Further, the peripherals perform various operations like data input/output and/or data storage. These peripheral controllers are operated by the CPU. The peripheral controllers are operated based on clock frequencies provided from a clock controller connected to the CPU and each of the peripheral controllers. Usually, each peripheral controller may generate interrupts to the CPU. The CPU intervention is provided to the interrupts i.e. the CPU services the interrupts. Presently, the CPU services the interrupts based on priority of the interrupts. The priority of the interrupts is set by using an interrupt controller which is connected between each of the peripheral controllers and the CPU. The interrupt controller prioritizes the interrupts received from the peripheral controller and set the interrupts like a precautionary interrupt or interrupts like data transfer completion of a low speed peripheral to low priority. In cases when the peripheral controllers issue the interrupts, the peripheral controller goes to a wait state waiting for the interrupts to be processed by the CPU. At such a stage, the clock controller provides the clock frequencies with the same rate to the peripheral controllers. As a result of such operation, power is consumed for the peripheral controller. For example, in normal scenario, the high priority interrupts are processed first than the low priority interrupts. While the interrupts from peripheral which are prioritized as low are not being processed, peripheral controller is waiting for the CPU to take action on such interrupts. At such a stage, the clock power is consumed as normal peripheral operation since same clock frequency is provided to the peripheral. In such a case, power consumed during this waiting period is same as normal peripheral operation. For example, in a typical complex SoC designs, there could be few hundreds of interrupts that needs CPU intervention. Hence, to process a low priority interrupt it might take up to few milliseconds. During such period, the peripheral controller, which generated low priority interrupt, is waiting for the CPU intervention and clock frequency given to the peripheral controller is running at full speed. As an example, consider a Serial Peripheral Interfaces (SPI) peripheral which is in a master mode. Upon receiving requested data for reading or writing, the SPI peripheral issues the interrupts and waits for the CPU to take an action. If the CPU is busy with other tasks, the clock frequency given by the clock controller to the SPI is still running in full speed even the SPI peripheral is in the wait state i.e. the SPI peripheral is not performing any task during such period. At such a stage, dynamic power is consumed by the clock controller (clock tree build from a clock source) to the peripheral and at the peripheral controllers (flops) in the SoC. There is necessary to reduce the power consumption of the SoC.
In one conventional method, the power consumption is reduced by reducing the clock frequencies to the peripheral controllers by reducing the clock frequencies or turning off the clock controller dynamically when feasible. However, such slowing down the clock frequencies or turning off the clock controller is achieved upon receiving instructions from the CPU. Particularly, the CPU first determines the type of the interrupts needs to be processed. Then, the CPU intimates the clock controller to slow down the clock frequencies or turn off the clock controller as per the type of the interrupts. Such a way of determining the type of the interrupts and then intimating to the clock controller is very time consuming and may result in long wait period for the clock controller and/or the peripheral controllers and needs additional software code and may be additional logic to indicate the peripheral state.
In one conventional method, a power management logic is implemented which firstly determines state of the peripheral controllers based on events generated by the peripheral controllers. When the events indicate that a peripheral controller has a lack of activity for a given period of time, a request is sent to the peripheral controller by the power management logic to enter into a power saving state. The peripheral controller then responds by sending an acknowledge signal. This handshaking is typically necessary to avoid uncompleted, pending transfers or tasks (e.g., pending FIFO or bus transfers). When the power management logic receives the acknowledge signal, indicating that the peripheral controller is ready to go into a power reduction state, the power management logic gates off or slows down the clock provided to the peripheral controller. However, such a way of determining the state of the peripheral controller and then reducing the clock frequencies is time consuming and needs additional power management logic built in the peripheral controller logic.